In general, tests are mainly classified into two types, i.e., product tests and prove (or function) tests. The product test screens for product failures and sorts out articles of good quality from defects that can occur during wafer-processing, an assembly process, etc.
The prove test confirms whether or not the function or performance of a manufactured DRAM meets design specification. The product test is frequently performed during a shipping process, and thus there is required high throughput in the product test. The purpose of the prove test is to shorten a development period and raise the completion degree of the product by thoroughly carrying out the prove test in a research and development period.
If finding out the defects occurring during manufacturing processes by means of the product test, or finding out that the function of the actual product does not meet with the design specification, a predetermined analysis such as a failure analysis is performed for accurately diagnosing reasons for failure. In particular, it is important to diagnose where the defects occur in the DRAM beyond question.
The DRAM test measures three kinds of characteristics, i.e., DC, AC and function, by using a measurement system such as a memory test. As one part of the function test, a burn-in test is performed after a semiconductor chip is packaged. The burn-in test is performed such that excessive stress is exerted upon the whole DRAM. That is, a voltage and an ambient temperature higher than for conditions of actual use are imposed upon the DRAM in order to find out initial defects in its early stages.
The cells sorted out as defects through the test may be repaired for performing normal operations. In other words, the defective cells are replaced with redundancy cells. Furthermore, a predetermined operational condition, which is arbitrarily set using experimental data, is applied to the passed cells sorted out through the test during DRAM operation.
However, if there is a significant number of detects corresponding to several bits or higher, it is impossible to repair the wafer chip. Thus, this chip cannot be used. As a result, the package cost of the chip and the time for the burn-in test after packaging have been unnecessarily consumed.
In addition, this problem may becomes more serious in a highly integrated device so that the burn-in test becomes more and more important in order to accurately detect the defective cells vulnerable to the wafer burn-in test before the package process. In the wafer burn-in test, it is important to appropriately exert the stress on a portion where the defect may occur in adjacent cells.
FIG. 1 is a block diagram of a conventional circuit for a wafer burn-in test.
The circuit for the wafer burn-in test includes a decoder 10, a wafer burn-in reset (WBI) unit 20, a trigger generation unit 30, and a plurality of latch units 40 to 46.
The decoder 10 decodes input signals WA<9>, WA<10> and WA<11> to output test mode setting signals TDCOFF, TAWL, TEWL, TOWL, T2RBE, T2RBO and TSAE. The WBI reset unit 20 outputs a wafer burn-in reset signal RESETB in response to the output of the decoder 10 or a power-up signal PWU_B of an initial operation. The trigger generation unit 30 outputs a trigger signal TRIGP in response to an input signal WA<8>.
In addition, the plurality of latch units 40 to 46 latch the test mode setting signals TDCOFF, TAWL, TEWL, TOWL, T2RBE, T2RBO and TSAE in response to the wafer burn-in reset signal RESETB and the trigger signal TRIGP, to thereby output test mode control signals TDCOFFW, TAWLW, TEWLW, TOWLW, T2RBEW, T2RBOW and TSAEW.
FIG. 2 is a circuit diagram of the latch unit 40 to 46 of FIG. 1. Herein, the structures of all the latch units 40 to 46 are identical to one another so that description will be only focused on one latch unit 40, for example.
The latch unit 40 includes NAND gates ND1 to ND3 and inverters INV1 and INV2. The NAND gate ND1 performs a NAND operation on input signals IN1 and IN2. Herein, the input signals IN1 and IN2 denote the test mode setting signal TDCOFF and the trigger signal TRIGP, respectively.
The NAND gates ND2 and ND3 form a latch circuit. That is, the output of the NAND gate ND2 is input through one terminal of the other NAND gate ND3, and vice versa. The NAND gate ND2 performs a NAND operation on the output of the NAND gate ND1 and the output of the NAND gate ND3. The NAND gate ND3 performs a NAND operation on the output of the NAND gate ND2 and wafer burn-in reset signal RESETB. The inverters IV1 and IV2 delay the output of the NAND gate ND2 to output the output signal OUT. Herein, the output signal corresponds to the test control signal TDCOFFW.
In the latch unit of FIG. 2, when the input signals are activated to ‘high’, the output of the NAND gate ND1 is latched at the NAND gates ND2 and ND3. Accordingly, the latch unit 40 maintains the output signal OUT to be ‘high’ until the wafer burn-in reset signal RESETB is input thereto.
FIG. 3 is a block diagram of a conventional circuit for a programmable stress test.
The conventional circuit for the programmable stress test includes a plurality of latch units 50 to 55, and a reset unit 56. The plurality of latch units 50 to 55 latch a programmable test signal TEST generated according to the test mode code which occurs when the programmable test mode is selected, mode select signals TRG1 to TRG6 setting respective different modes, and a reset signal TWLRSTB, to thereby output the test control signals TAWLT, TEWLT, TOWLT, T2RBET, T2RBOT, and TSAET. The reset signal TWLRSTB is a signal generated according to the test mode code which is generated when the programmable test mode is selected.
The reset unit 56 outputs the reset signal TWLRSTB in response to the programmable test signal TSET, a mode select signal TRG7, and a reset control signal TRSTPB.
The detailed structure of each latch unit 50 to 55 is identical to that of FIG. 2. That is, when the programmable test signal TSET and the mode select signal TRG1 to TRG6 are activated to ‘high’, the latch unit maintains the output signal OUT to be ‘high’ until the wafer burn-in reset signal RESETB is input thereto. When the reset control signal TRSTPB is activated, the output signal OUT becomes ‘low’.
FIG. 4 is a circuit diagram of a conventional signal output unit 60.
The conventional signal output unit 60 includes a plurality of NOR gates NOR1 to NOR6, NAND gates ND4 and ND5, and a plurality of inverters IV3 to IV15. The signal output unit 60 performs a logic operation on the test control signals TAWLT, TEWLT, TOWLT, T2RBET, T2RBOT, and TSAET and the test control signals TAWLW, TEWLW, TOWLW, T2RBEW, T2RBOW, and TSAEW, so as to output predetermined output signals TEWL, TOWL, T2RBE, T2RBO, and TSAE.
In the conventional test mode controller, there are separately employed the wafer burn-in test circuit for controlling the wafer burn-in test mode operation, the programmable stress test circuit for controlling the programmable test mode operation, and the signal output unit 60 for combining the outputs of the wafer burn-in test circuit and the programmable stress test circuit. Therefore, an unnecessary circuit is used in the conventional test mode controller. The conventional test mode controller requires a large chip area, high current consumption, and limited operational speed.